I do not understand how the L2 cache is integrated and connected to the SBus on the Chipyard SoC. I have read up on the literature of the technologies used to, that the sysbus is generated via the TileLink interconnect standard. I simply cannot locate all of the souce code which aptly connects this all together
What I really am asking for is if anyone could help through providing links to all of the respective hardware modules which connect the TileBus in the Rocket tiles up to the system bus, and from the system bus to the L2 banks? It would be invaluable seeing the source code for the modules which allow for the bridging the Rocket cores TileBus to the L2 cache banks.
I have tried reviewing the source code, I know that the L2 is added and the hierarchical buses are included, however I am left with more questions with answers just through the sheer code complexity. Another question I have in mind is how is BankedL2Key connected to the L2 cache?
Where is source code which shows TileLink connecting the modules together?
Any support would be greatly invaluable