I have a shift register in my top module called Rrg and I want to instantiate Sbox module when Rrg(1) = '1' in the called EnCore module. I have warnings:
1)Condition in IF GENERATE must be static.
2)Uninitialized out port Do has no driver. This port will contribute value (U) to the signal network.
entity EncCore is
port (
di : in std_logic_vector(127 downto 0);
Rrg : in std_logic_vector(4 downto 0);
Do : out std_logic_vector(127 downto 0)
);
end EncCore;
architecture behavioral of EncCore is
begin
gen : if (Rrg(1)='1') generate
innergen : for i in 0 to 15 generate
sbox_inst : sbox
port map(
input_byte => di((i + 1)*8 - 1 downto i*8),
output_byte => Do((i + 1)*8 - 1 downto i*8)
);
end generate innergen;
end generate gen;
end architecture behavioral;
You cannot use IF..GENERATE for conditions, which shall be evaluated at run-time. IF..GENERATE (and FOR..GENERATE) are similar to the pre-processor instructions in C/C++. With these instructions you can direct, if some logic shall be included or to include it multiple times.
So these are compile-time instructions and therefore they have to be static (e.g. based on constants).
But there is a general problem with your code. You want to use the logic inside
sboxonly when Rrg(1)='1'. In software it is correct, to call a function only when its result is needed, but with a hardware description language like VHDL you have to think differently. It is not possible to change the hardware (or the FPGA configuration) during run-time, but the circuits for every part of your design has to be there right from the beginning, even if it shall be used only a single time during run-time.In principle it would be sufficient to just remove the IF..GENERATE condition, but maybe you want to mask the output when it is not valid or to flag to the outside, when the output can be used. This depends on what is happening outside of your entity...