I am instantiating two components within a top level file, where this implements a Phase Accumulator and LUT with an 8-bit FTW, to essentially create a simple DDS system. Mind you this is very simplified and is for testing purposes only.
The issue lies with two separate results where the Quartus VWF editor is correctly outputting the locations from the LUT (this is auto-configured with a ROM component from the MegaWizard tool) of which they are stored in this .mif file. I had read somewhere that the relative path may trigger ModelSim to throw an error or warning about this but have not encountered this.
The waveform signals from the built-in VWF on Quartus gives the following, which is correct:
ModelSim signals::
There is no output on data_out, so why are the results different?
The phase accumulator output is working correctly however, therefore does this issue lie with the testbench or architecture of the top-level file?
Top-Level:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.ALL;
library altera_mf;
library lpm;
use lpm.lpm_components.all;
-------------------------------------------------------------------------------
entity DDS_top is
PORT (
clk : in std_logic;
fsw_in : in std_logic_vector(7 downto 0);
pa_probe_out : out std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end DDS_top;
-------------------------------------------------------------------------------
architecture DDS_top_bhv of DDS_top is
component PA_comp
PORT
(
CLK : IN STD_LOGIC := '1';
FSW : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
component LUT_comp
PORT
(
CLK : IN STD_LOGIC := '1';
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
signal pa_data_out : std_logic_vector(7 downto 0) := (others => '0');
begin
phase_acc : PA_comp
PORT MAP (
CLK => clk,
FSW => fsw_in,
DATA_OUT => pa_data_out
);
pa_probe_out <= pa_data_out;
lut_rom : LUT_comp
PORT MAP (
CLK => clk,
DATA_IN => pa_data_out,
DATA_OUT => data_out
);
end DDS_top_bhv;
Testbench:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.ALL;
entity DDS_tb is
end DDS_tb;
architecture DDS_tb_bhv of DDS_tb is
signal clk : std_logic := '0';
signal fsw_in : std_logic_vector(7 downto 0) := (others => '0');
signal pa_probe_out : std_logic_vector(7 downto 0) := (others => '0');
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
constant clk_period : time := 10 ns;
begin
uut: entity work.DDS_top
port map (
clk => clk,
fsw_in => fsw_in,
pa_probe_out => pa_probe_out,
data_out => data_out
);
-- Clock process def.
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus_process: process
begin
fsw_in <= "00000001";
wait for 1000 ns;
fsw_in <= "00000010";
wait for 1000 ns;
assert false report "Simulation complete" severity note;
end process;
end DDS_tb_bhv;
Note that I have tried to move around the .mif file as I believe this isn't the issue. The issue may lie in the LUT component but as seen above it works as intended according to the Quartus VWF editor.
LUT_comp.vhd:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library altera_mf;
library lpm;
use lpm.lpm_components.ALL;
entity LUT_comp is
PORT (
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end LUT_comp;
architecture LUT_comp_bhv of LUT_comp is
-- ROM PHFQ
component rom_phfq
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
begin
-- MEM0 for full cycle
mem_init : rom_phfq
PORT MAP
(
address => data_in,
clock => clk,
q => data_out
);
end LUT_comp_bhv;
phfq_comp.vhd:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rom_phfq IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rom_phfq;
ARCHITECTURE SYN OF rom_phfq IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "mem_init.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
PA_comp.vhd:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library altera_mf;
library lpm;
use lpm.lpm_components.ALL;
entity PA_comp is
Port (
clk : in std_logic;
fsw : in std_logic_vector(7 downto 0); -- Assuming an 8-bit FTW
data_out : out std_logic_vector(7 downto 0)
);
end PA_comp;
architecture PA_comp_bhv of PA_comp is
signal add_out : std_logic_vector(7 downto 0) := (others => '0');
signal q_out : std_logic_vector(7 downto 0) := (others => '0');
begin
-- LPM_ADD_SUB for phase accumulator
addnsub : lpm_add_sub
generic map (
LPM_WIDTH => 8,
LPM_DIRECTION => "ADD"
)
port map (
DATAA => fsw,
DATAB => q_out,
RESULT => add_out
);
-- LPM_FF for phase accumulator
dff : lpm_ff
generic map (
LPM_WIDTH => 8,
LPM_FFTYPE => "DFF"
)
port map (
DATA => add_out,
CLOCK => clk,
Q => q_out
);
data_out <= q_out;
end PA_comp_bhv;
ModelSim transcript output:
** Warning: (vsim-3473) Component instance "mem_init : rom_phfq" is not bound.
Time: 0 ps Iteration: 0 Instance: /dds_tb/uut/lut_rom File: C:/altera/13.0sp1/projects/MWT-DDS-PROJECT/LUT_comp.vhd
** Warning: (vsim-8684) No drivers exist on out port /dds_tb/uut/lut_rom/data_out, and its initial value is not used.
Therefore, simulation behavior may occur that is not in compliance with
the VHDL standard as the initial values come from the base signal /dds_tb/data_out.
** Warning: (vsim-8684) No drivers exist on out port /dds_tb/uut/data_out, and its initial value is not used.
Therefore, simulation behavior may occur that is not in compliance with
the VHDL standard as the initial values come from the base signal /dds_tb/data_out.
mem_init.mif file:
DEPTH = 256;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = BIN;
CONTENT
BEGIN
00 : 00000000;
01 : 00000011;
02 : 00000110;
03 : 00001001;
04 : 00001100;
05 : 00010000;
06 : 00010011;
07 : 00010110;
08 : 00011001;
09 : 00011100;
0A : 00011111;
0B : 00100010;
0C : 00100101;
0D : 00101000;
0E : 00101011;
0F : 00101110;
10 : 00110001;
11 : 00110011;
12 : 00110110;
13 : 00111001;
14 : 00111100;
15 : 00111111;
16 : 01000001;
17 : 01000100;
18 : 01000111;
19 : 01001001;
1A : 01001100;
1B : 01001110;
1C : 01010001;
1D : 01010011;
1E : 01010101;
1F : 01011000;
20 : 01011010;
21 : 01011100;
22 : 01011110;
23 : 01100000;
24 : 01100010;
25 : 01100100;
26 : 01100110;
27 : 01101000;
28 : 01101010;
29 : 01101011;
2A : 01101101;
2B : 01101111;
2C : 01110000;
2D : 01110001;
2E : 01110011;
2F : 01110100;
30 : 01110101;
31 : 01110110;
32 : 01111000;
33 : 01111001;
34 : 01111010;
35 : 01111010;
36 : 01111011;
37 : 01111100;
38 : 01111101;
39 : 01111101;
3A : 01111110;
3B : 01111110;
3C : 01111110;
3D : 01111111;
3E : 01111111;
3F : 01111111;
40 : 01111111;
41 : 01111111;
42 : 01111111;
43 : 01111111;
44 : 01111110;
45 : 01111110;
46 : 01111110;
47 : 01111101;
48 : 01111101;
49 : 01111100;
4A : 01111011;
4B : 01111010;
4C : 01111010;
4D : 01111001;
4E : 01111000;
4F : 01110110;
50 : 01110101;
51 : 01110100;
52 : 01110011;
53 : 01110001;
54 : 01110000;
55 : 01101111;
56 : 01101101;
57 : 01101011;
58 : 01101010;
59 : 01101000;
5A : 01100110;
5B : 01100100;
5C : 01100010;
5D : 01100000;
5E : 01011110;
5F : 01011100;
60 : 01011010;
61 : 01011000;
62 : 01010101;
63 : 01010011;
64 : 01010001;
65 : 01001110;
66 : 01001100;
67 : 01001001;
68 : 01000111;
69 : 01000100;
6A : 01000001;
6B : 00111111;
6C : 00111100;
6D : 00111001;
6E : 00110110;
6F : 00110011;
70 : 00110001;
71 : 00101110;
72 : 00101011;
73 : 00101000;
74 : 00100101;
75 : 00100010;
76 : 00011111;
77 : 00011100;
78 : 00011001;
79 : 00010110;
7A : 00010011;
7B : 00010000;
7C : 00001100;
7D : 00001001;
7E : 00000110;
7F : 00000011;
80 : 00000000;
81 : 11111101;
82 : 11111010;
83 : 11110111;
84 : 11110100;
85 : 11110000;
86 : 11101101;
87 : 11101010;
88 : 11100111;
89 : 11100100;
8A : 11100001;
8B : 11011110;
8C : 11011011;
8D : 11011000;
8E : 11010101;
8F : 11010010;
90 : 11001111;
91 : 11001101;
92 : 11001010;
93 : 11000111;
94 : 11000100;
95 : 11000001;
96 : 10111111;
97 : 10111100;
98 : 10111001;
99 : 10110111;
9A : 10110100;
9B : 10110010;
9C : 10101111;
9D : 10101101;
9E : 10101011;
9F : 10101000;
A0 : 10100110;
A1 : 10100100;
A2 : 10100010;
A3 : 10100000;
A4 : 10011110;
A5 : 10011100;
A6 : 10011010;
A7 : 10011000;
A8 : 10010110;
A9 : 10010101;
AA : 10010011;
AB : 10010001;
AC : 10010000;
AD : 10001111;
AE : 10001101;
AF : 10001100;
B0 : 10001011;
B1 : 10001010;
B2 : 10001000;
B3 : 10000111;
B4 : 10000110;
B5 : 10000110;
B6 : 10000101;
B7 : 10000100;
B8 : 10000011;
B9 : 10000011;
BA : 10000010;
BB : 10000010;
BC : 10000010;
BD : 10000001;
BE : 10000001;
BF : 10000001;
C0 : 10000001;
C1 : 10000001;
C2 : 10000001;
C3 : 10000001;
C4 : 10000010;
C5 : 10000010;
C6 : 10000010;
C7 : 10000011;
C8 : 10000011;
C9 : 10000100;
CA : 10000101;
CB : 10000110;
CC : 10000110;
CD : 10000111;
CE : 10001000;
CF : 10001010;
D0 : 10001011;
D1 : 10001100;
D2 : 10001101;
D3 : 10001111;
D4 : 10010000;
D5 : 10010001;
D6 : 10010011;
D7 : 10010101;
D8 : 10010110;
D9 : 10011000;
DA : 10011010;
DB : 10011100;
DC : 10011110;
DD : 10100000;
DE : 10100010;
DF : 10100100;
E0 : 10100110;
E1 : 10101000;
E2 : 10101011;
E3 : 10101101;
E4 : 10101111;
E5 : 10110010;
E6 : 10110100;
E7 : 10110111;
E8 : 10111001;
E9 : 10111100;
EA : 10111111;
EB : 11000001;
EC : 11000100;
ED : 11000111;
EE : 11001010;
EF : 11001101;
F0 : 11001111;
F1 : 11010010;
F2 : 11010101;
F3 : 11011000;
F4 : 11011011;
F5 : 11011110;
F6 : 11100001;
F7 : 11100100;
F8 : 11100111;
F9 : 11101010;
FA : 11101101;
FB : 11110000;
FC : 11110100;
FD : 11110111;
FE : 11111010;
FF : 11111101;
END;
This has been resolved by adding the
phfq_comp.vhdto the project library in ModelSim, as this component was automatically created by the MegaWizard tool so I did not even think of adding this to the project library. Therefore, is it best practise to add all.vhdcomponents to a ModelSim project? I assumed it would have had scope of instantiated components.