With all FPGA tools I have used so far: Intel Quartus Prime, Xilinx Vivado, Microsemi Libero SoC, it always takes the same amount of time whenever I run synthesis. What I would expect is that the synthesis takes long the first time and subsequently, as long as only small change is done in the code, it should take small amount of time. However, even if I have changed nothing and run synthesis, it still takes the full amount of time.
Is synthesis in these tools designed to clean everything and start from scratch each time? Why isn't incremental synthesis the default option? Please note that I am talking about synthesis and not fitter here.
FPGA synthesis defaults to building the entire chip every time. The reason for this is performance/optimization. There may be optimizations (area, speed, power) across hierarchical boundaries which could be made, that will not occur when isolated individual modules are synthesized.
There is a work flow which supports the build of only parts of the design. Its generally called incremental synthesis. UG901 is the Xilinx synthesis guide:
ug901-vivado-synthesis/Incremental-Synthesis
This should tell you what to do for the 7-series and beyond, even for the smaller parts.
There is a parallel Intel/Altera related doc here:
Incremental_bestpractices
There is a parallel microsemi document here:
incremental microsemi
Search the doc for incremental
An observation is that the larger vendors have more detailed documentation, and will have the best descriptions of how to do what suits your desired work flow.
If you are doing a module level work, then set up a separate synthesis for that module only (or a subset of modules needed to accomplish the behavior) to save the wall time of building the entire chip. The module only synthesis will be much faster (wall time) than the entire chip build. There is a synthesis mode to tell the tools to build the module without pads (pads affect performance). Its called out-of-context synthesis in the same document. Its good practice to synthesize a new module by itself first, so that you know its utilization, and ballpark performance before adding the module to the full chip build. I like to see that synthesis infers the primitives I modeled (BRAM, DSP blocks, LUT RAM etc). Also, create a clock constraint for the module, to determine if it can close timing. Performance numbers of an out of context synthesis will be optimistic compared to its use in the full chip. In the out of context synthesis the part is under-utilizing the parts resources, so its a somewhat artificial. Its useful though because if the module won't close timing in the OOC synthesis build, its not going to close timing in the full chip build.