VHDL getting a std_logic_vector out of an array of std_logic_vector

Question

I have a Problem. I have an array of std_logic_vector and I input a value unsinged(3 downto 0) and I want to use value as the Index of the array.

So far so good but I should get a std_logic_vector out of the array and put in the Output segments (which is also a std_logic_vector with the same size) but I get the error:

> can't match type conversion with type array type "std_logic_vector"

here is my Code:

> library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

entity getarrayvalue is
port(
        value : in unsigned(3 downto 0);
        clk : in std_logic;
        segments : out std_logic_vector(6 downto 0)
    );
end entity;

architecture v1 of getarrayvalue is
    type rom_type is array(0 to 9) of std_logic_vector(6 downto 0);
    signal rom: rom_type :=("1111110","0110000","1101101","1111001","0110011","1011011","1011111","1110000","1111111","1111011");
    signal val_i: integer;

    val_i <= to_integer(value); 

    process(clk)
    begin
        if rising_edge(clk) then
            segments <= rom_type(val_i);
        end if;
    end process;

end architecture;

Does anyone know how to fix this problem ? Thanks!