What will be the circuit for the counter with oscillating 1s (1000, 0100, 0010, 0001, 0010, 0100)?

Question

I have a basic understanding of custom counter. I know of a method to implement (8,4,2,1,2,4) counter i.e. using FSM, but I am not able to figure out how the circuit will get implemented?

Answer 1

This is at best marginally to do with programming but it may be better on one of the other sites where you'll no doubt get a better answer than this one.

However, in terms of an actual answer (whatever its shortcomings), this is difficult to do because each state does not wholly dictate the following state. By that, I mean there is no way to tell whether the pattern 0010 should be followed by 0100 (going left) or 0001 (going right).

However, there is a way to do this with a six-bit rotating shift register ^(a) as follows:

    b5 b4 b3 b2 b1 b0
+->  1  0  0  0  0  0 --+
|                       |
+-----------------------+

Then, you combine the bits to generate actual result bits:

b5       -> r3
b4 OR b0 -> r2
b3 OR b1 -> r1
b0       -> r0

That way you see the repeated pattern:

b5 b4 b3 b2 b1 b0 | b5 b4 ...
r3 r2 r1 r0 r1 r2 | r3 r2 ...

And, if you want some delay at the ends, you simply use an eight-bit shift register with slightly different combining. such that it lingers for twice as long on r3 and r0:

b7 OR b0 -> r3
b6 OR b1 -> r2
b5 OR b2 -> r1
b4 OR b3 -> r0

This gives:

b7 b6 b5 b4 b3 b2 b1 b0 | b7 b6 ...
r3 r2 r1 r0 r0 r1 r2 r3 | r3 r2 ...

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^(a) Although that link seems to specify non-rotating shift registers, it should be a simple matter to create a rotating one just by feeding the output of the rightmost bit back into the leftmost one.