2d array structure flattened into registers?

Question

In my verilog code I have an array declaration such that:

reg [8:0] mem [1024:0] ;

In the procedural block, I have this

always @(posedge clk) 
         for (i = 0; i < 8; i=i+1) begin
                mem[wr_address[i]] = data_in[i];
         end
end  

What ends up happening is my synthesis tool flattens this memory into an array of registers. I believe the reason is multiple reads in one clock cycle. What are ways I can avoid this issue while sill maintaining multiple writes in one clock cycle?

Answer 1

A BRAM usually can only access one or two ports at a time. The behavior you have described maps to flat set of bit registers. If you want a BRAM, you need to change the behavior to map the the functionality a BRAM provides. That is it can only access one element per read or write cycle.