Synthesis error in Vivado: [Synth 8-3380] loop condition does not converge after 2000 iterations

Question

module Delay_Module (
  input wire clk,
  input wire [3:0] data_in,
  input wire [7:0] delay_cycles,
  output reg [3:0] output_data
);
  reg [4:0] counter = 0;
  reg [3:0] memory [0:47];
  integer i;
  integer j;
  reg flag;
  initial begin
    for(j=0; j<48;j = j+1)begin
      memory[j]<=4'b0000; 
    end
    output_data <=0;  
    flag <= 1;
  end    
  always @(posedge clk ) begin
      if (flag == 1) begin
        for(i = delay_cycles-1; i >= 0; i = i - 1 )begin       
        memory[i+1] <= memory[i];
        output_data <= memory[delay_cycles-2];
        memory[0]<=data_in;
        end
      end          
end       
endmodule

I have to design a delay module, that stores data for delay_cycles time gpio inputs in memory and then outputs the stored data. The maximum value for delay_cycles is 48, same as memory size.

Answer 1

For synthesis, Vivado likely expects the loop to execute a constant number of times, but your for loop uses a variable delay_cycles in the start condition.

You declared a counter variable, but did not use it. You could implement a counter instead of using the for loop.

Answer 2

Usually synthesis does not work well with the loop which results in a variable number of iterations. In your case it is, due to the dynamic 'delay_cycles'. There is no good way to represent such a loop in (static) hardware.

The usual way to work around the issue is to create a loop with max (static) number of iterations and limit its actions to the range provided. The following example shows a possible solution. In addition, last two statements from the original loop make no much sense and should be removed from it.

     for(i = 47; i >= 0; i = i - 1 )begin  
        if (i < delay_cycle) begin     
           memory[i+1] <= memory[i];
         end
     end
     output_data <= memory[delay_cycles-2];
     memory[0]<=data_in;