I'm currently writing the code of a hardware accelerator in Verilog 2001, and a question has arisen to which I could not find an answer (maybe I don't know how to search for it):
- There's a simple sequential logic:
always @(posedge clk) begin
reg_q <= reg_d;
end
- There's a FSM doing some stuff:
always @* begin
...
reg_d = reg_q;
case(...) begin
...
end
...
end
And here is the question:
I have a simple 1-bit register
Athat under certain circumstances alternates between 1 and 0.The next state of the register
reg_qdepends on some variablefooand its dependency coincides with the bit change ofA. So, there are two things I could do but I don't know whether they are the same or they can produce some differences, let's say in the power consumption of the accelerator, or the area of the circuit. Will it generate the same circuit upon synthesis? Below the two options:
Multiplication:
reg_d = reg_q + (foo)*(A)
If-statement:
reg_d = reg_q
if(A) begin
reg_d = reg_q + (foo)
end
It's my first time asking here and I'm sorry if it's a repeated or non-relevant question.
This is all combinational logic, it generates the same boolean equations resulting in the same hardware. As long as you don't write code that creates additional latches, there will be no differences in power/area.