Clock Wizard IP affects Critical Path

Question

I am using Virtex-7 Evaluation board which has 200Mhz clock. My design has a critical path less than 4ns. I am trying to use clock wizard IP to generate 120MHZ clock from the input clock of 200MHz. However, I faced with failing timing after implementation. I look through timing summary and it seems that the critical path does not change while I have a large negative slack. I am wondering why this happen? Why there is large negative slack while the critical path remain the same?