Xilinx Virtex6 block ram width

Question

I'm confused about Virtex-6 BlockRAM.

I want to implement a BRAM with 15 bit address (32,768 words) and 12 bit write and read data per word. When I explore the implemented design, I founded that 12 BlockRAM are used for this. Does this mean each BRAM in a Virtex-6 has 1 bit data?!

What is the data width and capacity of each BlockRAM in a Virtex-6?

Answer 1

Each embedded BlockRAM (RAMB36E1) has 36 KiBit. It can also be split into two 18 KiBit primitives (RAMB18E1).

The internal organisation is 1024 × (32+4). 1024 rows with 4 bytes + 4 parity bits.

The BlockRAM macro has a variable layout from 32.768 × 1 up to 512 × 72, which is also depending on the mode: single port, simple dual port or true dual port.

Here is the full list of address to data width ratios:

• 64 Ki x 1, (cascaded adjacent BlockRAMs)
• 32 Ki x 1,
• 16 Ki x 2,
• 8 Ki x 4,
• 4 Ki x 8,
• 4 Ki x 9,
• 2 Ki x 16,
• 2 Ki x 18,
• 1 Ki x 32
• 1 Ki x 36 or
• 512 x 64 (simple dual-port mode) and
• 512 x 72 (simple dual-port mode)

See:

• the Virtex-6 Memory Resource User Guide [UG363] or
• the Virtex-6 HDL Library Guide [UG623]

for more details.

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When I explore the implemented design, I founded that 12 BlockRAM are used for this. Does this mean each BRAM in a Virtex-6 has 1 bit data?!

The used area (memory size) is equal to other organizations, but using 12 × (32.768 × 1) doesn't require multiplexers to combine the 12 BlockRAMs. This saves resources and is faster.