I m trying to synthetize any simple project in ISE for virtex 6. When I generated my synthesis report ,no minimum period was calculated

Question

I am running a project on xilinx 14,1 in virtex 6 . I generated synthesis report. while viewing i couldn't find minimum period.. please help?

Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: 15.397ns

Maximum output required time after clock: 0.562ns

Maximum combinational path delay: No path found

WHAT IS NEEDED FOR maximum frequency to be calculated automatically.

Answer 1

Continue through PAR, run "Analyze Post-Place & Route Static Timing", bottom of report will give you max frequency for your PAR design

Maybe add a timing constraint for the clock for good measure: "User constraints" >> "Create Timing Constraints" and put some value for the clock.