Error : Identifier 'q' is not readable in architecture of T Flip Flop

Question

I am trying to model a T Flip Flop using VHDL.

library ieee;
use ieee.std_logic_1164.all;
entity tff is
    port (
        clk: std_logic;
        t: in bit;
        q: out bit;
        qbar: out bit);
end tff;

architecture tff_arch of tff is
begin
    process(clk)
    begin
        if (clk = '1' and t = '1')
        then
            q <= not q;
            qbar <= not qbar;
        end if;
    end process;
end tff_arch;

But the error i am getting is

Error: CSVHDL0168: tff.vhdl: (line 17): Identifier 'q' is not readable
Error: CSVHDL0168: tff.vhdl: (line 18): Identifier 'qbar' is not readable

The reason of error i think is, i am using "not q", when q has not been initialized. Correct me here, if i am wrong.

And what to do to get around this problem? I have modeled D Flip flop and its test bench waveform correctly using Symphony EDA free version.

Answer 1

q is an output of the entity.

You can't read an output. It's that simple.

You need an internal version that you use for the feedback loop, and then q <= local_q;

Answer 2

Can't remember VHDL very well, but this might give you a clue:

The problem is that q is only a signal out of your entity, so there is nothing to access when you try to read it.

So, to not solve your homework, think of it this way:

Either you need to have q as an input in order to access it (probably not what you want) or you need to store q (or at least next value of q) internally. This can be done by specifying q (or q_next) as a signal in the architecture part. For example:

architecture tff_arch of tff is
  signal q_next: std_logic;
begin

and so on. The same goes for your qbar signal.

Answer 3

In the old days you couldn't read an output, so you had to either:

• make it an inout (which is a bit unpleasant as you are fudging the direction you really mean, just so you can read it) - this works, but is not widely used in industry (as far as I'm aware)
• make it a buffer, but that had downsides (prior to VHDL-2002) in that you have to make all the rest of the hierarchy of that signal driven by buffers. Almost never used in my experience.
• use and intermediate signal (which you can read) and then use an assignment to set the output to the value of that signal. This is the idiomatic way of doing it amongst practising engineers.

Since VHDL-2008 you can read output ports (although the stated intention of this is for it only to be used for verification purposes). You'll probably need a tool switch to enable VHDL-2008 mode. (And it may be that your particular simulator/synthesiser still doesn't support VHDL-2008, which shows the staggering pace of development in the EDA tools world!)