fork join algorithm on fpga

Question

I want to transfer a fork-join problem in fpga. Fork-join in the sense that there will be many small components (> 100) accessing a memory component, processing input data (a few 32-bit vectors) for small amount of cycles (~50) without interactions among them and then returning the data for accessing another memory. Does this sound a case where ,in terms of interconnections, i should use a traditional bus solution or i should shift to those NoC-based structures that are offered in system level tools (Qsys altera)?

Answer 1

Bus connection based on star topology will cause routing problems in this case when number of endpoints is big. If data can be processed sequential then I could recommend to build custom packet based sequential network.

Processing elements (PE) can be connected in pipeline, with data traffic passing through all of PEs in streaming fashion. Then each PE will save and process only its portion from data stream and pass other data to next PE.