In x86_64 architecture, if I modify a PTE in the page table, when will it be sync to TLB?

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I am designing an optimistic concurrency control mechanism to address TLB shootdowns for a specific application. The approach operates on the following principles:

The application manages data at the granularity of pages. Each page header contains the virtual address of the page. Access to any page requires first checking the virtual address tag located in the page's header. In the event of a page fault, the system can reassign physical pages from others without triggering a TLB flush. Due to the optimistic nature of this method, incorrect mappings in the page table can be identified. If the virtual address matches, access continues as normal. If there is a mismatch, the page must be reloaded, and the Page Table Entry (PTE) updated. At this juncture, an outdated and invalid TLB entry may exist because we avoid TLB flushing when reassigning its physical page. After reloading the data and updating its PTE to point to a different physical page, the PTE is corrected, but the TLB entry may still be incorrect. Is a TLB flush necessary in this step?

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