The page table will be saved in memory and accessed during the page walk process after TLB miss. Will this portion of memory be treated as ordinary data and enter the traditional L1-D/L2/L3 cache?
If so[1][2], considering that these caches themselves require physical addresses for hit checking[3], which in turn rely on page tables for address translation, has a circular dependency been generated?
If not, will this portion of memory be marked as "uncached"?