Multiple Flip Flop device

Question

I'm trying to write a VHDL code that represents an image diagram. I'm new to VHDL so I used a lot of conditionals for it to work. However, I'm having problems with the preset and clear inputs, I used if and elsif in order to know which one preset or clear is working, but I keep receiving this error:

Asynchronous Preset equation not allowed error for Q

My code is:

library ieee;
USE ieee.std_logic_1164.all;

entity FF is
    port(
            clk: in std_logic;
            ctrl : in std_logic_vector(1 downto 0);
            R,S,D,J,K,T,PS,CL: in std_logic;
            Q,QN : out std_logic);
    end FF;
    
architecture FF_arq of FF is
     signal tmp:std_logic;
 begin
    process(clk,ctrl,PS,CL)
        begin
            if PS='0' then
                tmp<='1';
            elsif CL='0' then
                tmp<='0';
            elsif (rising_edge(clk))then
                if ctrl="00" then
                    if R='0' and S='0' then
                        tmp<=tmp;
                    else if R='1' and S='0' then
                        tmp<='0';
                    else if R='0' and S='1' then
                        tmp<='1';
                    else
                        tmp<='-';
                    end if;
                    end if;
                    end if;
                else if ctrl="01" then
                    if D='0' then
                        tmp<='0';
                    else if D='1' then
                        tmp<='1';
                    else
                        tmp<='-';
                    end if;
                    end if;
                else if ctrl="10" then
                    if J='0' and K='0'then
                        tmp<=tmp;
                    else if J='1' and K='1' then
                        tmp<= not tmp;
                    else if J='1' and K='0' then
                        tmp<='1';
                    else
                        tmp<='0';
                    end if;
                    end if;
                    end if;
                else
                    if T='0' then
                        tmp<=tmp;
                    else 
                        tmp<= not tmp;
                    end if;
                end if;
                end if;
                end if;
            end if;                 
    end process;
    Q<= tmp;
    QN<= not tmp;
end FF_arq;

This is the diagram:

Answer 1

Tryed to short some things up, maybe there are some better solutions.

library ieee;
USE ieee.std_logic_1164.all;

entity FF is
    port(
            clk: in std_logic;
            ctrl : in std_logic_vector(1 downto 0);
            R,S,D,J,K,T,PS,CL: in std_logic;
            Q,QN : out std_logic);
    end FF;
    
architecture FF_arq of FF is
    signal tmp : std_logic := '0';
    signal RS : std_logic_vector(1 downto 0) := (others => '0');
    signal JK : std_logic_vector(1 downto 0) := (others => '0');
 begin
 
    Q <= tmp;
    QN <= not(tmp);
 
    process(clk,PS,CL)
        begin
            if PS='0' then
                tmp<='1';
            elsif CL='0' then
                tmp<='0';
            elsif (rising_edge(clk))then
            
                RS(1) <= R;
                RS(0) <= S;
                JK(1) <= J;
                JK(0) <= K;
            
                case ctrl is
                    when "00" => case RS is
                                    when "00" => tmp <= tmp;
                                    when "10" => tmp <= '0';
                                    when "01" => tmp <= '1';
                                    when others => tmp <= '-';
                                 end case;
                    when "01" => tmp <= D;
                    when "10" => case JK is
                                    when "00" => tmp <= tmp;
                                    when "11" => tmp <= not(tmp);
                                    when "10" => tmp <= '1';
                                    when others => tmp <= '0';
                                 end case;
                    when others =>  if T='0' then
                                        tmp <= tmp;
                                    else
                                        tmp <= not(tmp);
                                    end if;
                end case;
            end if;                 
    end process;
end FF_arq;

@ the moment i can´t check the code, so maybe there are some unwanted features...