Type error resolving infix expression when compiling simple decoder

Question

This is the code in vhdl:

library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER_TWO is
port
(
SW : in std_logic_vector(2 downto 1);
LD : out std_logic_vector(4 downto 1)
);
end DECODER_TWO;

architecture MY_FIRST_DECODER of DECODER_TWO is
begin
with SW select
 LD <= "1110" when "00", 
 LD <= "1101" when "01",
 LD <= "1011" when "10",
 LD <= "0111" when "11",
 LD <= "1111" when others;
end MY_FIRST_DECODER;

When I try to compile this very simple 2 to 4-bit decoder I get the error message, no matter what I do

# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(15): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(16): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(17): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(18): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(19): VHDL Compiler exiting

I can't see or understand what the problem is, since I don't get an error for '<=' in the first line, only line 2, 3, 4, and 5.