Altera Cyclone III onchip ram latency

Question

I have an issue with FPGA RAM. I want to make Z-buffering in my 3D renderer project. This involves one read and one conditional write access to memory.

Simultaneous read and write in one cycle gives wrong graphical results (data written to ram is displayed on screen). When I wait for 3 cycles graphical results are correct.

when st_render =>
    put_pixel_out_next <= '0';
    depth_buf_in <= depth_buf_out;

    if cnty <= render_rect_latch.y1 then
        if cntx < render_rect_latch.x1 then
            e0 := cross_product(cntx, cnty, triangle_latch(0), triangle_latch(1));
            e1 := cross_product(cntx, cnty, triangle_latch(1), triangle_latch(2));
            e2 := cross_product(cntx, cnty, triangle_latch(2), triangle_latch(0));


            if e0 <= 0 and e1 <= 0 and e2 <= 0 then
                 depth := (e0 * depths_in.z + e1 * depths_in.x + e2 * depths_in.y) / area_in;
                 depth_buf_in <= unsigned(std_logic_vector(depth + 127))(15 downto 0); -- ram write

                 state_next <= st_wait_0;
            end if;
            cntx_next <= cntx + 1;
        else
            cntx_next <= render_rect_latch.x0;
            cnty_next <= cnty + 1;
    end if;
    else
        ready_out_next     <= '1';
        put_pixel_out_next <= '0';
        state_next         <= st_idle;
    end if;

when st_wait_0 => -- good results with this delay
    state_next <= st_wait_1;

when st_wait_1 =>
    state_next <= st_wait_2;

when st_wait_2 =>
    color_out <= (
        r => std_logic_vector(depth_buf_out(7 downto 0) ), -- ram read
        g => std_logic_vector(depth_buf_out(7 downto 0)),
        b => std_logic_vector(depth_buf_out(7 downto 0))
     );

     put_pixel_out_next <= '1';
     state_next <= st_render;

I read that read and write could be done in single cycle. Is there any latency greater that one cycle in this FPGA architecture?