How to test J and B type RISCV instructions with random operands jumping to random memory locations?

Question

I am using Verilator to simulate Ibex RISCV core.

I have written a RISCV random instruction generator, which simply randomly generates RISCV instructions with random operands as well. All these generated instructions together compose a small assembly program.

This means the generator will absolutely generate J type and B type instructions with a large offset that leads to a very far memory location that exceeds the boundary of the program, where there is literally no valid instruction at all. And the processor does not know that so it keeps fetching illegal instructions after that destination address, which results in failed simulation. For example:

  f0:   77c00f13                li      t5,1916
  f4:   00000013                nop
  f8:   00271a93                slli    s5,a4,0x2
  fc:   da500ce3                beq     zero,t0,ffffff14 <__global_pointer$+0xffffe5a0>
 100:   0067dab3                srl     s5,a5,t1
 104:   00f19933                sll     s2,gp,a5
 108:   d55e2023                sw      s5,-704(t3)
 10c:   5504f113                andi    sp,s1,1360

let's assume the final instruction of this program is andi at the address of 0x10c. If beq at address 0xfc is true, pc is updated to a value that is outside this program (before or after, both can happen).

In this case, what am I supposed to do to prevent the processor fetching illegal instructions outside the memory region of this program? My plan is to make it fetch the instruction at 0x100 right after executing beq (same for other J and B type instuctions) instead of in other memory regions.