i had designed a 32 bit mac unit using VHDL in xilinx . now, i want to calculate the delay theoretically and compare with timing report obtained from xilinx
is there any specific procedure for calculating delay of the logic gate???
i had designed a 32 bit mac unit using VHDL in xilinx . now, i want to calculate the delay theoretically and compare with timing report obtained from xilinx
is there any specific procedure for calculating delay of the logic gate???
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