Adding skew to improve timing

Question

I want to improve the operating frequency of my design, In the register to register timing analysis I have observed a lot of delay in the combinational elements. This is impacting the timing of the circuit and the slack observed is about -0.3ns , I was wondering if I could add a skew to the destination register of about 3 ns (something like introducing a latency or adding a buffer in the clock tree towards this node). If this could be done, I would like to commands i should use in synopsys for this.

Thanks

Answer 1

What you are looking for is called useful skew. See this: http://www.slideshare.net/miaofei/snug-presentation-final4

and

http://rd.springer.com/chapter/10.1007/0-306-47823-4_8#page-1